1. Field of the Invention
This invention relates to a method for manufacturing a semiconductor device.
2. Background Art
The on-resistance of a vertical power MOSFET (metal oxide semiconductor field effect transistor) greatly depends on the electric resistance of its conduction layer (drift layer) portion. The dopant concentration determining the electric resistance of the drift layer cannot exceed a maximum limit, which depends on the breakdown voltage of the pn junction interface between the base layer and the drift layer.
Thus, there is a tradeoff between the device breakdown voltage and the on-resistance. Improving this tradeoff is important in reducing the power consumption of a power device. This tradeoff has a limit determined by the device material. Overcoming this limit is the way to realizing devices with low on-resistance beyond existing power semiconductor devices.
As an example MOSFET to solve this problem, a structure with p-type pillar layers and n-type pillar layers alternately arranged in the drift layer is known as a super junction structure (hereinafter referred to as SJ structure). In the SJ structure, a non-doped layer is artificially produced by equalizing the amount of charge (amount of impurities) contained in the p-type pillar layer with that contained in the n-type pillar layer. Thus, while holding a high breakdown voltage, a current is passed through the highly doped n-type pillar layer. Hence, a low on-resistance beyond the material limit can be realized.
Thus, the SJ structure can be used to achieve a balance between on-resistance and breakdown voltage beyond the material limit. A technique for forming p-type and n-type pillar layers is disclosed in JP-A 9-266311 (Kokai) (1997), for instance. In this technique, an n-type pillar layer is previously formed by epitaxial growth, and then partly etched away to form trenches in a striped configuration. A p-type pillar layer is buried in the etched trench by epitaxial growth, and the unwanted portion is polished away.
However, a void may remain in the actual p-type pillar layer when grown. Because the position of this remaining void is indeterminate, the void may appear on the polished surface even after the unwanted portion is polished. Thus, the polished surface of the SJ structure does not become flat, which results in decreasing the yield of semiconductor devices.